Reply To: Suggested refinements

[Michael P. Flaga]

Yes, the hardware is actually controlling the chipselect. If one of the prescribed allowed pins. Where the code builds (aka packs) a 32 bit word that contains the mask of chipselects, LASTXFER bit/flag, and data value to send into the SPI_TDR register. All necessary to transmit the byte, as opposed to the ATmega328 that has different SPDR and SPCR. Where as the code is simply writing the TDR as opposed to writing the digital out directly. So basically the same affect and cycles.

The Big advantage to having hardware queued control of the CS would be in using the DMA, to move data while non blocking. Only need to start the transfer, go and do something else and come back and check if it was done. And this is where hard CS support is useful. Where hear the spi.tranfer blocks for each byte, before until it is ready and after until it is sent.

I just remembered while, looking at it again. I recall and see that only pins D10, D4, D52 and D78 of the Due can be used with this queue controlled method for Chip Selects. Where the SFE MP3 shield uses D6, D7 and D9 as chip selects. So it become academic, without jumper’ing.